TECHNICAL PAPERS: Gas Turbines: Controls, Diagnostics, and Instrumentation

Integrated in-Flight Fault Detection and Accommodation: A Model-Based Study

[+] Author and Article Information
Randal T. Rausch1

 GE Global Research, 1 Research Circle, Niskayuna, NY 12309rausch@research.ge.com

Kai F. Goebel

 GE Global Research, 1 Research Circle, Niskayuna, NY 12309goebel@email.arc.nasa.gov

Neil H. Eklund

 GE Global Research, 1 Research Circle, Niskayuna, NY 12309eklund@research.ge.com

Brent J. Brunell

 GE Global Research, 1 Research Circle, Niskayuna, NY 12309brunelbr@research.ge.com


Corresponding author.

J. Eng. Gas Turbines Power 129(4), 962-969 (Jan 04, 2007) (8 pages) doi:10.1115/1.2720517 History: Received September 09, 2005; Revised January 04, 2007

In-flight fault accommodation of safety-critical faults requires rapid detection and remediation. Indeed, for a class of safety-critical faults, detection within a millisecond range is imperative to allow accommodation in time to avert undesired engine behavior. We address these issues with an integrated detection and accommodation scheme. This scheme comprises model-based detection, a bank of binary classifiers, and an accommodation module. The latter biases control signals with pre-defined adjustments to regain operability while staying within established safety limits. The adjustments were developed using evolutionary algorithms to identify optimal biases off-line for multiple faults and points within the flight envelope. These biases are interpolated online for the current flight conditions. High-fidelity simulation results are presented showing accommodation applied to a high-pressure compressor fault on a commercial, high-bypass, twin-spool, turbofan engine throughout the flight envelope.

Copyright © 2007 by American Society of Mechanical Engineers
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Figure 1

High-level architecture of detection and accommodation strategy

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Figure 2

Fault block diagram

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Figure 3

Fault classification scheme

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Figure 4

Engine parameters for single HPC fault simulation

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Figure 5

Histogram representing HPC fault trends

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Figure 6

Optimization architecture

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Figure 7

Med. fault (med TRA, high Alt, med Mach)

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Figure 8

Med. fault (very low TRA, low Alt, med Mach)

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Figure 9

Med. fault (med TRA, med Alt, very high Mach)

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Figure 10

Small fault (med TRA, low Alt, med Mach)

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Figure 11

Med. fault (med TRA, low Alt, very low Mach)

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Figure 12

Large fault (med TRA, low Alt, med Mach)



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